《网上多核众核系统的网络结构和映射算法Hu,Wei,Shi,Qing》[60M]百度网盘|pdf下载|亲测有效

图书基本信息
图书名称	网上多核/众核系统的网络结构和映射算法（英文版）
作者	Hu,Wei,Shi,QingSong,Wang... 著
定价	98元
出版社	科学出版社
ISBN	9787030644169
出版日期	2020-06-01
字数
页码	171
版次
装帧	平装
开本	16开
商品重量

内容提要

Chip multiprocessors have beethe mainstream iputer architecture. Such processors have more thaone core oa single chip to obtaihigher performance and lower power consumption. However， whemore and more cores are integated onto the chip， the increasing number of cores makes the municatiobee the center of the on-chip architecture. It haee a new challenge ohow to utilize these integrated cores ia single area with high efficiency. Thiook provides the explorative research othe above problems. There are four maitopics discussed ithiook. The first is the hybrid on-chip structure， which consists of the on-chip work and the on-chip bus. The bus is used to connect the local neiours， and the work is used to connect the remote nodes. And thethiook provides discussions oon-chip structure and optimizations including the dynamic reconfigurable work， the
　　desigof critical path-driverouters and the transmissiobypass optimization. They are used to achieve better performance. The third topic focuses othe on-chip memory design， which is called the on-chip worked memory system. The memories are connected by the work with distributed memory management units. At last， the mapping algorithms are discussed， which aim to map the tasks to the on-chip cores with high efficiency and low-power consumption. Thiook has provided some works inwork-based manycore systems. The designs and algorithms provided ithiook are potential
　　solutions for multicore/manycore architecture. It cabe used as the reference for future work and for the researchers who focus othe puter architecture.

Contents
Preface
1 Introductioto NoC 1
1.1 Development of Computer Architecture 1
1.2 Chip Multiprocessor 3
1.3 On-chip Structure and NoC 6
1.4 Summary 10
2 Hybrid Network and Bus On-Chip Interconnectio11
2.1 Introductio11
2.2 Hybrid On-chip Interconnectiowith NoC and the Bus 13
2.2.1 Motivatio13
2.2.2 On-Chip Structure 14
2.2.3 Support for Thread Scheduling 15
2.2.4 Experiments and Results 16
2.3 Dynamic Configurable On-Qiip Network with the Hybrid Bus and Networks 18
2.3.1 Motivatio18
2.3.2 Bus/NoC Hybrid Interconnectio19
2.3.3 Component Desig21
2.3.4 Experiment and Results 23
2.4 Summary 28
3 On-Chip Structure and Optimizations 30
3.1 Introductio30
3.2 Dynamic Reconfigurable Networks for I/O-Supported Parallel Applications 31
3.2.1 Background 31
3.2.2 Architecture Desig33
3.2.3 Implementatio37
3.2.4 Experiments and Analysis 42
3.3 Critical Path-DriveRouters for the On-Chip Network 46
3.3.1 Background 46
3.3.2 Motivatio48
3.3.3 Architecture 51
3.3.4 Implementatio53
3.3.5 Experiments and Analysis 56
3.4 TransmissioBypass Optimizatiofor On-Chip Cores 60
3.4.1 Background 60
3.4.2 Motivatio61
3.4.3 Desig62
3.4.4 Implementatio65
3.4.5 Experiments and Analysis 68
3.5 Summary 75
4 On-Chip Networked Memory System for NoC 77
4.1 Introductio77
4.2 Network MaiMemory Architecture for NoC 78
4.2.1 Background 78
4.2.2 Motivatio80
4.2.3 Basic NMM Architecture 81
4.2.4 Management of NMM and Software Model 85
4.2.5 Experiments and Analysis 87
4.3 Distributed Memory Management Units Architecture for NoC 94
4.3.1 Background 94
4.3.2 Motivatio98
4.3.3 Architecture Model 100
4.3.4 Experiments and Analysis 104
4.4 Summary 108
5 Efficient Task Mapping Algorithm with Low-Power Desigfor NoC 110
5.1 Introductio110
5.2 Efficient Task Mapping Algorithm with Power-Aware Optimizatiofor NoC 111
5.2.1 Background Ill
5.2.2 Motivatio112
5.2.3 System Model 114
5.2.4 Proposed Algorithm Desig119
5.2.5 Experiments and Analysis 129
5.3 Energy-Efficient Desigof the Microkernel-Based On-Chip OS for NoC 133
5.3.1 Background 133
5.3.2 Motivatio134
5.3.3 DesigOverview 136
5.3.4 Distributed On-Chip Operating System 139
5.3.5 Experimental Results and Analysis 144
5.4 Summary 151
6 Conclusions 153
References 156

网上多核众核系统的网络结构和映射算法Hu,Wei,Shi,Qing pdf下载

内容简介

网上多核众核系统的网络结构和映射算法Hu,Wei,Shi,Qing pdf下载

内容简介

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