计算机组织与结构-性能设计第8版

基本信息

书名:计算机组织与结构-性能设计 第8版       定价：99元      ISBN：9787121170607

作者:(美)斯托林斯　著      出版社：电子工业出版社   

参考信息（以实物为准）

出版日期：2012-07-01      字数：1441000  

页码：774      版次：       

装帧：平装      开本：16开

编辑

《计算机组织与结构——性能设计(第8版英文版)》是一本反映当代计算机系统结构主流技术和技术进步的教材，先前版本曾4次荣获Textand Academic Authors Association颁发的计算机科学与工程教材奖。作者斯托林斯以Intelx86系列通用处理器和ARM系列嵌入式处理器作为主要考察实例贯穿全书，将当代计算机系统性能设计问题和计算机组织与结构的基本概念及原理紧密联系起来。通过介绍计算机的发展与演变引人性能评价和性能设计的概念，然后以自顶而下的方式逐层展开介绍计算机系统、存储器体系结构、I/O及互连、计算机算术、指令集体系结构设计及其实现技术、控制器设计，还介绍处理器的各种并行组织技术。

内容提要

《计算机组织与结构——性能设计(第8版英文版)》以Intelx86系列通用处理器和ARM系列嵌入式处理器作为主要考察实例，将当代计算机系统性能设计问题和计算机组织与结构的基本概念及原理紧密联系。首先介绍计算机的发展与演变，引人性能评价和性能设计的概念，然后以自顶而下的方式逐层展开介绍计算机系统、存储器体系结构、I/O及互连、计算机算术、指令集体系结构的设计及其实现技术、控制器设计，还介绍了处理器的各种并行组织技术。本书特色在于探讨和揭示面向性能的各种设计博弈和实现考量，追逐性能极大化的同时顾及系统整体的性能平衡。《计算机组织与结构——性能设计(第8版英文版)》可以作为高等院校信息领域的本科生、研究生和教师的双语教学教材或教学参考书，对于从事计算机研究与开发的技术人员，也是一本颇具指导意义的参考读物。本书由斯托林斯(WilliamStallings)著。

目录

Chapter 0 Reader’s Guide
0.1 Outline of the Book
0.2 A Roadmap for Reade and I tructo
0.3 Why Study Computer Organization and Architecture
0.4 Inter and Web Resources
PART ONE OVERVIEW
Chapter 1 Introductio
1.1 Organization and Architecture
1.2 Structure and Functio
1.3 Key Terms and Review Questio
Chapter 2 Computer Evolution and Performance
2.1 A Brief History of Compute
2.2 Designing for Performance
2.3 The Evolution of the Intel x86 Architecture
2.4 Embedded Systems and the ARM
2.5 Performance Assessment
2.6 Remended Reading and Web Sites
2.7 Key Terms, Review Questio , and Problems
PART TWO THE PUTER SYSTEM
Chapter 3 A TopLevel View of Computer Function andInterconnectio
3.1 Computer Components
3.2 Computer Functio
3.3 Interconnection Structures
3.4 Bus Interconnectio
3.5 PCI
3.6 Remended Reading and Web Sites
3.7 Key Terms, Review Questio , and Problems
Appendix 3A Timing Diagrams
Chapter 4 Cache Memory
4.1 Computer Memory System Overview
4.2 Cache Memory Principles
4.3 Elements of Cache Desig
4.4 Pentium 4 Cache Organizatio
4.5 ARM Cache Organizatio
4.6 Remended Reading
4.7 Key Terms, Review Questio , and Problems
Appendix 4A Performance Characteristics of TwoLevel Memories
Chapter 5 Internal Memory Technology
5.1 Semiconductor Main Memory
5.2 Error Correctio
5.3 Advanced DRAM Organizatio
5.4 Remended Reading and Web Sites
5.5 Key Terms, Review Questio , and Problems
Chapter 6 External Memory
6.1 Magic Disk
6.2 RAID
6.3 Optical Memory
6.4 Magic Tape
6.5 Remended Reading and Web Sites
6.6 Key Terms, Review Questio , and Problems
Chapter 7 Input/Output
7.1 External Devices
7.2 I/O Modules
7.3 Programmed I/O
7.4 InterruptDriven I/O
7.5 Direct Memory Access
7.6 I/O Channels and Processo
7.7 The External Interface: FireWire and Infiniband
7.8 Remended Reading and Web Sites
7.9 Key Terms, Review Questio , and Problems
Chapter 8 Operating System Support
8.1 Operating System Overview
8.2 Scheduling
8.3 Memory Management
8.4 Pentium Memory Management
8.5 ARM Memory Management
8.6 Remended Reading and Web Sites
8.7 Key Terms, Review Questio , and Problems
PART THREE THE CENTRAL PROCESSING UNIT
Chapter 9 Computer Arithmetic
9.1 The Arithmetic and Logic Unit (ALU)
9.2 Integer Representatio
9.3 Integer Arithmetic
9.4 FloatingPoint Representatio
9.5 FloatingPoint Arithmetic
9.6 Remended Reading and Web Sites
9.7 Key Terms, Review Questio , and Problems
Chapter 10 I truction Sets: Characteristics and Functio
10.1 Machine I truction Characteristics
10.2 Types of Operands
10.3 Intel x86 and ARM Data Types
10.4 Types of Operatio
10.5 Intel x86 and ARM Operation Types
10.6 Remended Reading
10.7 Key Terms, Review Questio , and Problems
Appendix 10A Stacks
Appendix 10B Little, Big, and BiEndia
Chapter 11 I truction Sets: Addressing Modes and Formats
11.1 Addressing
11.2 x86 and ARM Addressing Modes
11.3 I truction Formats
11.4 x86 and ARM I truction Formats
11.5 Assembly Language
11.6 Remended Reading
11.7 Key Terms, Review Questio , and Problems
Chapter 12 Processor Structure and Functio
12.1 Processor Organizatio
12.2 Register Organizatio
12.3 The I truction Cycle
12.4 I truction Pipelining
12.5 The x86 Processor Family
12.6 The ARM Processor
12.7 Remended Reading
12.8 Key Terms, Review Questio , and Problems
Chapter 13 Reduced I truction Set Compute (RISCs)
13.1 I truction Execution Characteristics
13.2 The Use of a Large Register File
13.3 CompilerBased Register Optimizatio
13.4 Reduced I truction Set Architecture
13.5 RISC Pipelining
13.6 MIPS R4000
13.7 SPARC
13.8 The RISC ve us CISC Controve y
13.9 Remended Reading
13.10 Key Terms, Review Questio , and Problems
Chapter 14 I tructionLevel Parallelism and Supe calarProcesso
14.1 Overview
14.2 Design Issues
14.3 Pentium 4
14.4 ARM CortexA8
14.5 Remended Reading
14.6 Key Terms, Review Questio , and Problems
PART FOUR THE CONTROL UNIT
Chapter 15 Control Unit Operatio
15.1 Microoperatio
15.2 Control of the Processor
15.3 Hardwired Implementatio
15.4 Remended Reading
15.5 Key Terms, Review Questio , and Problems
Chapter 16 Microprogrammed Control
16.1 Basic Concepts
16.2 Microi truction Sequencing
16.3 Microi truction Executio
16.4 TI 8800
16.5 Remended Reading
16.6 Key Terms, Review Questio , and Problems
PART FIVE PARALLEL ORGANIZATION
Chapter 17 Parallel Processing
17.1 The Use of Multiple Processo
17.2 Symmetric Multiprocesso
17.3 Cache Coherence and the MESI Protocol
17.4 Multithreading and Chip Multiprocesso
17.5 Cluste
17.6 Nonuniform Memory Access Compute
17.7 Vector Computatio
17.8 Remended Reading and Web Sites
17.9 Key Terms, Review Questio , and Problems
Chapter 18 Multicore Compute
18.1 HardwarePerformance Issues
18.2 Software Performance Issues
18.3 Multicore Organizatio
18.4 Intel x86 Multicore Organizatio
18.5 ARM11 MPCore
18.6 Remended Reading and Web Sites
18.7 Key Terms, Review Questio , and Problems
Appendix A Projects for Teaching Computer Organizatio
and Architecture
A.1 Interactive Simulatio
A.2 Research Projects
A.3 Simulation Projects
A.4 Assembly Language Projects
A.5 Reading/Report Assignments
A.6 Writing Assignments
A.7 Test Bank
Appendix B Assembly Language and Related Topics
B.1 Assembly Language
B.2 Assemble
B.3 Loading and Linking
B.4 Remended Reading and Web Sites
B.5 Key Terms, Review Questio , and Problems
ONLINE CHAPTERS
Chapter 19 Number Systems
19.1 The Decimal System
19.2 The Binary System
19.3 Converting between Binary and Decimal
19.4 Hexadecimal Notatio
19.5 Key Terms, Review Questio , and Problems
Chapter 20 Digital Logic
20.1 Boolean Algebra
20.2 Gates
20.3 Combinational Circuits
20.4 Sequential Circuits
20.5 Programmable Logic Devices
20.6 Remended Reading and Web Site
20.7 Key Terms and Problems
Chapter 21 The IA64 Architecture
21.1 Motivatio
21.2 General Organizatio
21.3 Predication, Speculation, and Software Pipelining
21.4 IA64 I truction Set Architecture
21.5 Itanium Organizatio
21.6 Remended Reading and Web Sites
21.7 Key Terms, Review Questio , and Problems
ONLINE APPENDICES
Appendix C Hash Tables
Appendix D Victim Cache Strategies
D.1 Victim Cache
D.2 Selective Victim Cache
Appendix E Interleaved Memory
Appendix F International Reference Alphabet
Appendix G Virtual Memory Page Replacement Algorithms
Appendix H Recu ive Procedures
H.1 Recu io
H.2 Activation Tree Representatio
H.3 Stack Processing
H.4 Recu ion and Iteratio
Appendix I Additional I truction Pipeline Topics
I.1 Pipeline Reservation Tables
I.2 Reorder Buffe
I.3 Scoreboarding
I.4 Tomasulo’s Algorithm
Appendix J Linear Tape Open Technology
Appendix K DDR SDRAM
Glossary
References
Index

作者介绍

WilliamStallings，作为一名顾问、讲师和17本(不包括再版)著作的作者，WilliamStallings是计算机界的一位巨擘。本书第四版获得了由美国教科书与高等院校作者协会(Text and Academic AuthoAssociation)颁发的2002年度计算机与工程图书奖。他还因其大量作品获得了很多其他的奖项。他从NotreDame获得电子工程硕士学位后，在MIT获得计算机科学博士学位。他维护了一个面向计算机科学的学生资源网站：：//WilliamStallings./StudentSupport.。他在PrenticeHall公司出版的所有图书均可以在网站：//.prenhall.上找到。

文摘

序言